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| SPICE Device Model SUM110P04-05 Vishay Siliconix P-Channel 40-V (D-S) MOSFET CHARACTERISTICS * P-Channel Vertical DMOS * Macro Model (Subcircuit Model) * Level 3 MOS * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 74144 S-52522Rev. A, 12-Dec-05 www.vishay.com 1 SPICE Device Model SUM110P04-05 Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Condition Simulated Data 2.8 982 0.0040 126 -0.88 Measured Data Unit VGS(th) ID(on) rDS(on) gfs VSD VDS = VGS, ID = - 250 A VDS -5 V, VGS = -10 V VGS = -10 V, ID = -20 A VDS = -15 V, ID = -20 A IS = -20 A V A 0.0041 75 -80 S V Drain-Source On-State Resistancea Forward Transconductancea Diode Forward Voltagea Dynamicb Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge c c Ciss Coss Crss Qg Qgs Qgd VDS = -20 V, VGS = -10 V, ID = -20 A VGS = 0 V, VDS = -25 V, f = 1 MHz 9687 1524 844 195 48 42 11300 1510 1000 185 48 42 nC pF Gate-Source Charge Gate-Drain Charge c Notes a. Pulse test; pulse width 300 s, duty cycle 2%. b. Guaranteed by design, not subject to production testing. c. Independent of operating temperature. www.vishay.com 2 Document Number: 74144 S-52522Rev. A, 12-Dec-05 SPICE Device Model SUM110P04-05 Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) Document Number: 74144 S-52522Rev. A, 12-Dec-05 www.vishay.com 3 |
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